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FEATURES

LTC2453 Easy-to-Use, Ultra-Tiny, Differential, 16-Bit ADC With I2C Interface DESCRIPTION
The LTC(R)2453 is an ultra-tiny, fully differential, 16-bit, analog-to-digital converter. The LTC2453 uses a single 2.7V to 5.5V supply and communicates through an I2C interface. The ADC is available in an 8-pin, 3mm x 2mm DFN package. It includes an integrated oscillator that does not require any external components. It uses a delta-sigma modulator as a converter core and has no latency for multiplexed applications. The LTC2453 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude lower than conventional delta-sigma converters. Additionally, due to its architecture, there is negligible current leakage between the input pins. The LTC2453 can sample at 60 conversions per second, and due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. The LTC2453 includes continuous internal offset and full-scale calibration algorithms which are transparent to the user, ensuring accuracy over time and over the operating temperature range. The converter has external REF+ and REF- pins and the differential input voltage range can extend up to (VREF+ - VREF-). Following a single conversion, the LTC2453 can automatically enter a sleep mode and reduce its power to less than 0.2A. If the user reads the ADC once a second, the LTC2453 consumes an average of less than 50W from a 2.7V supply.
Integral Nonlinearity, VCC = 3V
2.0 1.5 VCC = 3V VREF+ = 3V VREF- = 0V
VCC Differential Input Range 16-Bit Resolution (Including Sign), No Missing Codes 2LSB Offset Error 4LSB Full-Scale Error 60 Conversions Per Second Single Conversion Settling Time for Multiplexed Applications Single-Cycle Operation with Auto Shutdown 800A Supply Current 0.2A Sleep Current Internal Oscillator--No External Components Required 2-Wire I2C Interface Ultra-Tiny 3mm x 2mm DFN Package
APPLICATIONS

System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
TYPICAL APPLICATION
2.7V TO 5.5V 0.1F 0.1F IN+ 10k 10k IN- 10k R 0.1F REF- REF+ VCC SCL LTC2453 SDA 2-WIRE I2C INTERFACE 10F
INL (LSB)
1.0 0.5 0 -0.5 -1.0 TA = -45C, 25C, 90C
GND
-1.5 -2.0
2453 TA01
-3
-2 -1 1 2 0 DIFFERENTIAL INPUT VOLTAGE (V)
3
2453 G02
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LTC2453 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW GND 1 REF- 2 REF+ 3 VCC 4 9 8 7 6 5 SDA SCL IN+ IN-
Supply Voltage (VCC) ................................... -0.3V to 6V Analog Input Voltage (VIN+, VIN-) .. -0.3V to (VCC + 0.3V) Reference Voltage (VREF+, VREF-) .. -0.3V to (VCC + 0.3V) Digital Voltage (SDA, SCL) ............ -0.3V to (VCC + 0.3V) Storage Temperature Range................... -65C to 150C Operating Temperature Range LTC2453C ................................................ 0C to 70C LTC2453I ............................................. -40C to 85C
DD8 PACKAGE 8-LEAD (3mm x 2mm) PLASTIC DFN C/I GRADE TJMAX = 125C, JA = 76C/W (NOTE 4) EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE 0C to 70C -40C to 85C LTC2453CDDB#TRMPBF LTC2453CDDB#TRPBF LDBQ 8-Lead Plastic (3mm x 2mm) DFN LTC2453IDDB#TRMPBF LTC2453IDDB#TRPBF LDBQ 8-Lead Plastic (3mm x 2mm) DFN TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Transition Noise Power Supply Rejection DC
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
CONDITIONS (Note 3) (Note 4)

MIN 16
TYP 2 2 0.02 0.01 0.02 1.4 80
MAX 10 10 0.02
UNITS Bits LSB LSB LSB/C % of FS LSB/C VRMS dB
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LTC2453 ANALOG INPUTS AND REFERENCES
SYMBOL VIN VIN
+ -
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
PARAMETER Positive Input Voltage Range Negative Input Voltage Range Positive Reference Voltage Range Negative Reference Voltage Range Overrange/Underrange Voltage, IN+ Overrange/Underrange Voltage, IN- IN+, IN- Sampling Capacitance IN+ DC Leakage Current IN- DC Leakage Current VIN = GND (Note 8) VIN = VCC (Note 8) VIN = GND (Note 8) VIN = VCC (Note 8) VREF = 3V (Note 8)

CONDITIONS

MIN 0 0 VCC - 2.5 0
TYP
MAX VCC VCC VCC VCC - 2.5
UNITS V V V V LSB LSB pF
VREF+ VREF- VOR+, VUR+ VOR-, VUR- CIN IDC_LEAK(IN+) IDC_LEAK(IN-)
VREF+ - VREF- 2.5V VREF+ - VREF- 2.5V VREF = 5V, VIN- = 2.5V (See Figure 2) VREF = 5V, VIN+ = 2.5V (See Figure 2)

8 8 0.35 -10 -10 -10 -10 -10 1 1 1 1 1 50 10 10 10 10 10
nA nA nA nA nA nA
IDC_LEAK(REF+, REF-) REF+, REF- DC Leakage Current ICONV Input Sampling Current (Note 5)
POWER REQUIREMENTS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Sleep
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
CONDITIONS

MIN 2.7
TYP
MAX 5.5
UNITS V A A
800 0.2
1200 0.6
I2C INPUTS AND OUTPUTS
SYMBOL VIH VIL II VHYS VOL IIN CI CB PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 2, 7)
CONDITIONS

MIN 0.7VCC
TYP
MAX 0.3VCC
UNITS V V A V V A pF pF
-10 0.05VCC
10 0.4 1
Hysteresis of Schmidt Trigger Inputs Low Level Output Voltage (SDA) Input Leakage Capacitance for Each I/O Pin Capacitance Load for Each Bus Line
(Note 3) I = 3mA 0.1VCC VIN VCC

10 400
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LTC2453 I2C TIMING CHARACTERISTICS
SYMBOL tCONV fSCL tHD(SDA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF tOF tSP PARAMETER Conversion Time SCL Clock Frequency Hold Time (Repeated) START Condition LOW Period of the SCL Pin HIGH Period of the SCL Pin Set-Up Time for a Repeated START Condition Data Hold Time Data Set-Up Time Rise Time for SDA/SCL Signals Fall Time for SDA/SCL Signals Set-Up Time for STOP Condition Bus Free Time Between a Stop and Start Condition Output Fall Time VIHMIN to VILMAX Input Spike Suppression Bus Load CB 10pF to 400pF (Note 6) (Note 6) (Note 6)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 2, 7)
CONDITIONS

MIN 13 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 20 + 0.1CB
TYP 16.6
MAX 23 400
UNITS ms kHz s s s s
0.9 300 300
s ns ns ns s s
250 50
ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. VREF = VREF+ - VREF-, VREFCM = (VREF+ + VREF-)/2, FS = VREF+ - VREF-; VIN = VIN+ - VIN-, -VREF VIN VREF; VINCM = (VIN+ + VIN-)/2. Note 3. Guaranteed by design, not subject to test.
Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. Guaranteed by design and test correlation. Note 5. Input sampling current is the average input current drawn from the input sampling network while the LTC2453 is converting. Note 6. CB = capacitance of one bus line in pF. Note 7. All values refer to VIH(MIN) and VIL(MAX) levels. Note 8. A positive current is flowing into the DUT pin.
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity, VCC = 5V
2.0 1.5 1.0 INL (LSB) INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 -5 -4 -3 -2 -1 0 1 2 3 4 DIFFERENTIAL INPUT VOLTAGE (V) 5 TA = -45C, 25C, 90C VCC = 5V VREF+ = 5V VREF- = 0V 2.0 1.5 1.0 VCC = 3V VREF+ = 3V VREF- = 0V
(TA = 25C, unless otherwise noted) Maximum INL vs Temperature
2.0 VCC = VREF+ = 5V, 4.1V, 3V
Integral Nonlinearity, VCC = 3V
1.5 INL (LSB) TA = -45C, 25C, 90C
0.5 0 -0.5 -1.0 -1.5 -2.0 -3
1.0
0.5
1 2 0 DIFFERENTIAL INPUT VOLTAGE (V)
-2
-1
3
2453 G02
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
2453 G03
2453 G01
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LTC2453 TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs Temperature
5 4 OFFSET ERROR (LSB) 3 2 1 VCC = VREF+ = 5V 0 -1 -50 GAIN ERROR (LSB) 5
(TA = 25C, unless otherwise noted) Transition Noise vs Temperature
3.0 2.5 2.0 1.5 1.0 0.5 0 -50 VCC = 4.1V
Gain Error vs Temperature
4 VCC = VREF+ = 3V VCC = VREF+ = 4.1V VCC = VREF+ = 3V VCC = VREF+ = 4.1V
3
2
TRANSITION NOISE RMS (V)
VCC = 5V
VCC = 3V
1 VCC = VREF+ = 5V
-25
0 25 50 TEMPERATURE (C)
75
100
2453 G04
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
2453 G05
-25
0 25 50 TEMPERATURE (C)
75
100
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Transition Noise vs Output Code
3.0 2.5 2.0 1.5 1.0 0.5 0 -32768 VCC = VREF+ = 5V VCC = VREF+ = 3V 1200
Conversion Mode Power Supply Current vs Temperature
250 60Hz OUTPUT SAMPLE RATE CONVERSION CURRENT (A) 1000 800 600 400 200 0 -50 VCC = 3V VCC = 4.1V SLEEP CURRENT (nA) VCC = 5V 200
Sleep Mode Power Supply Current vs Temperature
TRANSITION NOISE RMS (V)
VCC = 5V 150 VCC = 4.1V
100
50
VCC = 3V
-16384
0 16384 OUTPUT CODE
32768
2453 G07
-25
0 25 50 TEMPERATURE (C)
75
100
2453 G08
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
2453 G09
Average Power Dissipation vs Temperature, VCC = 3V
10000 AVERAGE POWER DISSIPATION (W) 0
Power Supply Rejection vs Frequency at VCC
21 VCC = 4.1V VREF+ = 2.7V VREF- = 0V VIN+ = 1V VIN- = 2V 20 CONVERSION TIME (ms)
Conversion Time vs Temperature
1000
25Hz OUTPUT SAMPLE RATE REJECTIOIN (dB)
-20
VCC = 3V 19 VCC = 4.1V 18 VCC = 5V 17 16 15
10Hz OUTPUT SAMPLE RATE 100 1Hz OUTPUT SAMPLE RATE
-40
-60
10 -80
1 -50
-25
0 25 50 TEMPERATURE (C)
75
100
2453 G10
-100 1 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M 10M
14 -50
-25
50 25 0 TEMPERATURE (C)
75
100
2453 G12
2453 G11
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LTC2453 PIN FUNCTIONS
GND (Pin 1): Ground. Connect to a ground plane through a low impedance connection. REF- (Pin 2), REF+ (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, remains more positive than the negative reference input, REF-, by at least 2.5V. The differential reference voltage (VREF = REF+ to REF-) sets the full-scale range. VCC (Pin 4): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10F capacitor in parallel with a low-series-inductance 0.1F capacitor located as close to the part as possible. IN- (Pin 5), IN+ (Pin 6): Differential Analog Input. SCL (Pin 7): Serial Clock Input of the I2C Interface. The LTC2453 can only act as a slave and the SCL pin only accepts external serial clock. Data is shifted into the SDA pin on the rising edges of SCL and output through the SDA pin on the falling edges of SCL. SDA (Pin 8): Bidirectional Serial Data Line of the I2C Interface. The conversion result is output through the SDA pin. The pin is high impedance unless the LTC2453 is in the data output mode. While the LTC2453 is in the data output mode, SDA is an open drain pull down (which requires an external 1.7k pull-up resistor to VCC). Exposed Pad (Pin 9): Ground. Must be soldered to PCB ground.
BLOCK DIAGRAM
3 REF+ 4 VCC
6
IN+
16-BIT A/D CONVERTER
I2C INTERFACE
SCL SDA
7 8
-
5 IN- 16-BIT A/D CONVERTER
DECIMATING SINC FILTER INTERNAL OSCILLATOR
2
REF-
1
GND
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LTC2453 APPLICATIONS INFORMATION
CONVERTER OPERATION Converter Operation Cycle The LTC2453 is a low-power, fully differential, delta-sigma analog-to-digital converter with an I2C interface. Its operation, as shown in Figure 1, is composed of three successive states: CONVERSION, SLEEP and DATA OUTPUT. Initially, at power up, the LTC2453 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by several orders of magnitude. The part remains in the sleep state as long it is not addressed for a read operation. The conversion result is held indefinitely in a static shift register while the part is in the sleep state.
POWER-ON RESET
edges of SCL, allowing the user to reliably latch data on the rising edge of SCL. A new conversion is initiated by a stop condition following a valid read operation, or by the conclusion of a complete read cycle (all 16 bits read out of the device). Power-Up Sequence When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2453 starts a conversion cycle and follows the succession of states described in Figure 1. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage VCC is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Ease of Use The LTC2453 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. The LTC2453 performs offset calibrations every conversion. This calibration is transparent to the user and has no effect upon the cyclic operation described previously. The advantage of continuous calibration is extreme stability of the ADC performance with respect to time and temperature. The LTC2453 includes a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. This allows external filter networks to interface directly to the LTC2453. Since the average input sampling current is 50nA, an external RC lowpass filter using a 1k and 0.1F results in <1LSB additional error. Additionally, there is negligible leakage current between IN+ and IN-.
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CONVERSION
SLEEP
NO
READ ACKNOWLEDGE
YES DATA OUTPUT
NO
STOP OR READ 16-BITS YES
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Figure 1. LTC2453 State Diagram
The device will not acknowledge an external request during the conversion state. After a conversion is finished, the device is ready to accept a read request. The LTC2453's address is hard-wired at 0010100. Once the LTC2453 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (SCL). There is no latency in the conversion result. The data output is 16 bits long and contains a 15-bit plus sign conversion result. Data is updated on the falling
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LTC2453 APPLICATIONS INFORMATION
Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage range for REF+ and REF- pins covers the entire operating range of the device (GND to VCC). For correct converter operation, VREF+ must be >(2.5V + VREF-). The LTC2453 differential reference input range is 2.5V to VCC. For the simplest operation, REF+ can be shorted to VCC and REF- can be shorted to GND. Input Voltage Range For most applications, VREF- (VIN+, VIN-) VREF+. Under these conditions the output code is given (see Data Format section) as 32768 * (VIN+ - VIN-)/(VREF+ - VREF-). The output of the LTC2453 is clamped at a maximum value of 32767 and clamped at a minimum value of -32768. The LTC2453 includes a proprietary system that can, typically, correctly digitize each input 8LSB above VREF+ and below VREF-, if the LTC2453's output is not clamped. As an example (Figure 2), if the user desires to measure a signal slightly below ground, the user could set VIN- = VREF- = GND, and VREF+ = 5V. If VIN+ = GND, the output code would be approximately 0. If VIN+ = GND - 8LSB = -1.22 mV, the output code would be approximately -8.
20 16 12 8 OUTPUT CODE 4 0 -4 -8 -12 -16 -20 -0.001 -0.005 0 VIN+/VREF+ 0.005 0.001 0.0015
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I2C INTERFACE The LTC2453 communicates through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the data line (SDA) LOW and never drive it HIGH. SDA must be externally connected to the supply through a pull-up resistor. When the data line is free, it is HIGH. Data on the I2C bus can be transferred at rates up to 100kbits/s in the Standard-Mode and up to 400kbits/s in the Fast-Mode. Each device on the I2C bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Devices addressed by the master are considered a slave. The address of the LTC2453 is 0010100. The LTC2453 can only be addressed as a slave. It can only transmit the last conversion result. The serial clock line, SCL, is always an input to the LTC2453 and the serial data line SDA is bidirectional. Figure 3 shows the definition of the I2C timing. The START and STOP Conditions A START (S) condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data transfer is finished, a STOP (P) condition is generated by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is free after a STOP is generated. START and STOP conditions are always generated by the master. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START timing is functionally identical to the START and is used for reading from the device before the initiation of a new conversion.
SIGNALS BELOW GND
Figure 2. Output Code vs VIN+ with VIN- = 0 and VREF- = 0
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LTC2453 APPLICATIONS INFORMATION
SDA tf tLOW tr tSU(DAT) tf tHD(SDA) tSP tr tBUF
SCL tHD(STA) S tSU(STA) Sr tSU(STO) P S
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tHD(DAT)
tHIGH
Figure 3. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
1 SCL 7 8 9 1 2 3 8 9 1 2 3 8 9
SDA
7-BIT ADDRESS
R
D15 SGN
D14 MSB
D13
D8
D7
D6
D5
D0 LSB
START BY MASTER SLEEP
ACK BY LTC2453
ACK BY MASTER DATA OUTPUT
NACK BY MASTER CONVERSION
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Figure 4. Read Sequence Timing Diagram
Data Transferring After the START condition, the I2C bus is busy and data transfer can begin between the master and the addressed slave. Data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA LOW or issue a Not Acknowledge (NAK) by leaving the SDA line HIGH impedance (the external pull-up resistor will hold the line HIGH). Change of data only occurs while the clock line (SCL) is LOW. Data Format After a START condition, the master sends a 7-bit address followed by a read request (R) bit. The bit R is 1 for a Read Request. If the 7-bit address matches the LTC2453's address (hard-wired at 0010100) the ADC is selected. When the device is addressed during the conversion state, it does not accept the request and issues a NAK by leaving the SDA line HIGH. If the conversion is complete, the LTC2453 issues an ACK by pulling the SDA line LOW.
Following the ACK, the LTC2453 can output data. The data output stream is 16 bits long and is shifted out on the falling edges of SCL (see Figure 4). The first bit output by the LTC2453 is the sign, which is 1 for VIN+ VIN- and 0 for VIN+ < VIN-. The next bit is the MSB (D14) and is followed by successively less significant bits (D13, D12...) until the LSB is output by the LTC2453. This sequence is shown in Figure 5. OPERATION SEQUENCE Continuous Read Conversions from the LTC2453 can be continuously read, see Figure 6. At the end of a read operation, a new conversion automatically begins. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not complete and a valid address selects the device, the LTC2453 generates a NAK signal indicating the conversion cycle is in progress.
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LTC2453 APPLICATIONS INFORMATION
S CONVERSION 7-BIT ADDRESS (0010100) SLEEP R ACK READ DATA OUTPUT P CONVERSION
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Figure 5. The LTC2453 Coversion Sequence
S CONVERSION
7-BIT ADDRESS (0010100) SLEEP
R
ACK
READ DATA OUTPUT
P CONVERSION
S
7-BIT ADDRESS (0010100) SLEEP
R ACK
READ DATA OUTPUT
P CONVERSION
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Figure 6. Consecutive Reading at the Same Configuration
S CONVERSION
7-BIT ADDRESS (0010100) SLEEP
R
ACK READ (OPTIONAL) DATA OUTPUT
P CONVERSION
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Figure 7. Start a New Conversion without Reading Old Conversion Result
Discarding a Conversion Result and Initiating a New Conversion It is possible to start a new conversion without reading the old result, as shown in Figure 7. Following a valid 7-bit address, a read request (R) bit, and a valid ACK, a STOP command will start a new conversion. PRESERVING THE CONVERTER ACCURACY The LTC2453 is designed to dramatically reduce the conversion result's sensitivity to device decoupling, PCB layout, antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels Due to the nature of CMOS logic, it is advisable to keep input digital signals near GND or VCC. Voltages in the range of 0.5V to VCC - 0.5V may result in additional current leakage from the part.
Driving VCC and GND In relation to the VCC and GND pins, the LTC2453 combines internal high frequency decoupling with damping elements, which reduce the ADC performance sensitivity to PCB layout and external components. Nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. A 0.1F, high quality, ceramic capacitor in parallel with a 10F ceramic capacitor should be connected between the VCC and GND pins, as close as possible to the package. The 0.1F capacitor should be placed closest to the ADC package. It is also desirable to avoid any via in the circuit path, starting from the converter VCC pin, passing through these two decoupling capacitors, and returning to the converter GND pin. The area encompassed by this circuit path, as well as the path length, should be minimized. Very low impedance ground and power planes, and star connections at both VCC and GND pins, are preferable. The VCC pin should have three distinct connections: the
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LTC2453 APPLICATIONS INFORMATION
VCC ILEAK REF+ ILEAK SIG+ VCC ILEAK IN+ ILEAK SIG- VCC ILEAK IN- ILEAK RSW 15k (TYP) CEQ 0.35pF (TYP) RSW 15k (TYP) VCC RS ILEAK IN+ CIN CPAR VCC RS ILEAK IN- CIN CPAR ILEAK ILEAK RSW 15k (TYP) CEQ 0.35pF (TYP) RSW 15k (TYP) CEQ 0.35pF (TYP)
+ -
ICONV
RSW 15k (TYP)
+ -
ICONV
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Figure 9. LTC2453 Input Drive Equivalent Circuit
VCC ILEAK REF- ILEAK
RSW 15k (TYP)
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package. The 0.1F capacitor should be placed closest to the ADC. Driving VIN+ and VIN- The input drive requirements can best be analyzed using the equivalent circuit of Figure 9. The input signal VSIG is connected to the ADC input pins (IN+ and IN-) through an equivalent source resistance RS. This resistor includes both the actual generator source resistance and any additional optional resistors connected to the input pins. Optional input capacitors CIN are also connected to the ADC input pins. This capacitor is placed in parallel with the ADC input parasitic capacitance CPAR. Depending on the PCB layout, CPAR has typical values between 2pF and 15pF. In addition, the equivalent circuit of Figure 9 includes the converter equivalent internal resistor RSW and sampling capacitor CEQ. There are some immediate trade-offs in RS and CIN without needing a full circuit analysis. Increasing RS and CIN can give the following benefits: 1) Due to the LTC2453's input sampling algorithm, the input current drawn by either VIN+ or VIN- over a conversion cycle is 50nA. A high RS * CIN attenuates the high frequency components of the input current, and RS values up to 1k result in <1LSB error.
Figure 8. LTC2453 Analog Input/Reference Equivalent Circuit
first to the decoupling capacitors described above, the second to the ground return for the input signal source, and the third to the ground return for the power supply voltage source. Driving REF+ and REF- A simplified equivalent circuit for REF+ and REF- is shown in Figure 8. Like all other A/D converters, the LTC2453 is only as accurate as the reference it is using. Therefore, it is important to keep the reference line quiet by careful low and high frequency power supply decoupling. The LT6660 reference is an ideal match for driving the LTC2453's REF+ pin. The LTC6660 is available in a 2mm x 2mm DFN package with 2.5V, 3V, 3.3V and 5V options. A 0.1F, high quality, ceramic capacitor in parallel with a 10F ceramic capacitor should be connected between the REF+/REF- and GND pins, as close as possible to the
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LTC2453 APPLICATIONS INFORMATION
2) The bandwidth from VSIG is reduced at the input pins (IN+, IN-). This bandwidth reduction isolates the ADC from high frequency signals, and as such provides simple antialiasing and input noise reduction. 3) Switching transients generated by the ADC are attenuated before they go back to the signal source. 4) A large CIN gives a better AC ground at the input pins, helping reduce reflections back to the signal source. 5) Increasing RS protects the ADC by limiting the current during an outside-the-rails fault condition. There is a limit to how large RS * CIN should be for a given application. Increasing RS beyond a given point increases the voltage drop across RS due to the input current, to the point that significant measurement errors exist. Additionally, for some applications, increasing the RS * CIN product too much may unacceptably attenuate the signal at frequencies of interest. For most applications, it is desirable to implement CIN as a high-quality 0.1F ceramic capacitor and RS 1k. This capacitor should be located as close as possible to the actual VIN package pin. Furthermore, the area encompassed by this circuit path, as well as the path length, should be minimized. In the case of a 2-wire sensor that is not remotely grounded, it is desirable to split RS and place series resistors in the ADC input line as well as in the sensor
10 8 6 4 INL (LSB) 2 0 -2 -4 -6 -8 -10 -5 -4 -3 -2 -1 0 1 2 3 4 DIFFERENTIAL INPUT VOLTAGE (V) 5 RS = 1k RS = 2k RS = 0 CIN = 0.1F VCC = 5V TA = 25C RS = 10k INL (LSB)
ground return line, which should be tied to the ADC GND pin using a star connection topology. Figure 10 shows the measured LTC2453 INL vs Input Voltage as a function of RS value with an input capacitor CIN = 0.1F. In some cases, RS can be increased above these guidelines. The input current is zero when the ADC is either in sleep or I/O modes. Thus, if the time constant of the input RC circuit = RS * CIN, is of the same order of magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. These considerations need to be balanced out by the input signal bandwidth. The 3dB bandwidth 1/(2RSCIN). Finally, if the recommended choice for CIN is unacceptable for the user's specific application, an alternate strategy is to eliminate CIN and minimize CPAR and RS. In practical terms, this configuration corresponds to a low impedance sensor directly connected to the ADC through minimum length traces. Actual applications include current measurements through low value sense resistors, temperature measurements, low impedance voltage source monitoring, and so on. The resultant INL vs VIN is shown in Figure 11. The measurements of Figure 11 include a capacitor CPAR corresponding to a minimum sized layout pad and a minimum width input trace of about 1 inch length.
10 CIN = 0 8 V = 5V CC 6 TA = 25C 4 2 0 -2 -4 -6 -8 -10 -5 -4 -3 -2 -1 0 1 2 3 4 DIFFERENTIAL INPUT VOLTAGE (V) 5 RS = 10k RS = 0 RS = 1k, 2k
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Figure 10. Measured INL vs Input Voltage, CIN = 0.1F, VCC = 5V, TA = 25C
Figure 11. Measured INL vs Input Voltage, CIN = 0, VCC = 5V, TA = 25C
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LTC2453 APPLICATIONS INFORMATION
0 INPUT SIGNAL ATTENUATIOIN (dB) 1.00 1.25 1.50
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0 -5 -10 -15 -20 -25 -30 -35 -40 -45
INPUT SIGNAL ATTENUATION (dB)
-20
-40
-60
-80
-100 0 2.5 5.0 7.5 INPUT SIGNAL FREQUENCY (MHz)
-50
0
60 120 180 240 300 360 420 480 540 600 INPUT SIGNAL FREQUENCY (Hz)
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Figure 12. LTC2453 Input Signal Attentuation vs Frequency
Figure 13. LTC2453 Input Signal Attenuation vs Frequency (Low Frequencies)
Signal Bandwidth, Transition Noise and Noise Equivalent Input Bandwidth The LTC2453 includes a sinc1 type digital filter with the first notch located at f0 = 60Hz. As such, the 3dB input signal bandwidth is 26.54Hz. The calculated LTC2453 input signal attenuation vs frequency over a wide frequency range is shown in Figure 12. The calculated LTC2453 input signal attenuation vs frequency at low frequencies is shown in Figure 13. The converter noise level is about 1.4VRMS and can be modeled by a white noise source connected at the input of a noise-free converter. On a related note, the LTC2453 uses two separate A/D converters to digitize the positive and negative inputs. Each of these A/D converters has 1.4VRMS transition noise. If one of the input voltages is within this small transition noise band, then the output will fluctuate one
bit, regardless of the value of the other input voltage. If both of the input voltages are within their transition noise bands, the output can fluctuate 2 bits. For a simple system noise analysis, the VIN drive circuit can be modeled as a single-pole equivalent circuit characterized by a pole location fi and a noise spectral density ni. If the converter has an unlimited bandwidth, or at least a bandwidth substantially larger than fi, then the total noise contribution of the external drive circuit would be: Vn = ni / 2 * fi Then, the total system noise level can be estimated as the square root of the sum of (Vn2) and the square of the LTC2453 noise floor (~1.4V2).
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13
LTC2453 TYPICAL APPLICATION
DC1266A Demo Board Schematic
V+ 3 LT6660 IN OUT 1 5V C3 1F R4 1.0 VCC C1 0.1F 3 6 C2 0.1F 5 C7 0.1F IN- REF C8 0.1F
-
JP1 EXT C9 1F
VCC
V+ 1 2 VUNREG 5V CS SCK/SCL MOSI/SDA MISO J1 EESCL EEVCC EESDA EEGND NC GND GND GND 3 8 13 TO CONTROLLER
C4 1F GND GND 2 4 E5 REF+
SCL SDA
6 4 7 5
C10 0.1F 4 VCC SCL LTC2453 SDA GND GND 1 9 8 7 R6 4.99k 1% R7 4.99k 1% 8 6 7 SCL WP 24LC025-I/ST 3 2 EXT JP2 GND 1 A2 A1 A0 GND 4 SDA 5 VCC
E1 IN+ E2 IN- E3 VCC E4 GND E6 REF-
R1 1k R9 1k C6 0.1F VCC
IN+
REF
+
11 10 R8 4.99k 1% C5 0.1F 9 12 14
2
2453 TA02
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LTC2453 PACKAGE DESCRIPTION
DDB Package 8-Lead Plastic DFN (3mm x 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
0.61 0.05 (2 SIDES) 0.70 0.05 2.55 0.05 1.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.20 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 0.10 (2 SIDES) R = 0.115 TYP 5 0.40 0.10 8
R = 0.05 TYP
PIN 1 BAR TOP MARK (SEE NOTE 6)
2.00 0.10 (2 SIDES) 0.56 0.05 (2 SIDES) 0.75 0.05
0.200 REF
4 0.25 0.05 2.15 0.05 (2 SIDES)
1 0.50 BSC
PIN 1 R = 0.20 OR 0.25 x 45 CHAMFER
(DDB8) DFN 0905 REV B
0 - 0.05
BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC2453 RELATED PARTS
PART NUMBER LT1236A-5 LT1461 LT1790 LTC1860/LTC1861 LTC1860L/LTC1861L LTC1864/LTC1865 LTC1864L/LTC1865L LTC2440 LTC2480 LTC2481 LTC2482 LTC2483 LTC2484 LTC2485 LTC6241 LT6660 LTC2450 LTC2450-1 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference, 2.5V Micropower Precision Reference in TSOT-23-6 Package 12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 16-bit, 3V, 1-/2-Channel 150ksps SAR ADC 24-Bit No Latency TMADC 16-Bit, Differential Input, No Latency ADC, with PGA, Temp. Sensor, SPI 16-Bit, Differential Input, No Latency ADC, with PGA, Temp. Sensor, I2C 16-Bit, Differential Input, No Latency ADC, SPI 16-Bit, Differential Input, No Latency ADC, I2C 24-Bit, Differential Input, No Latency ADC, SPI 24-Bit, Differential Input, No Latency ADC, I2C Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp Micropower References in 2mm x 2mm DFN Package, 2.5V, 3V, 3.3V, 5V Easy-to-Use, Ultra-Tiny 16-Bit ADC Easy-to-Use, Ultra-Tiny 16-Bit ADC COMMENTS 0.05% Max, 5ppm/C Drift 0.04% Max, 3ppm/C Drift 60A Max Supply Current, 10ppm/C Max Drift, 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V Options 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 200nVRMS Noise, 8kHz Output Rate, 15ppm INL Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy-Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package 550nVP-P Noise, 125V Offset Max 20ppm/C max drift, 0.2% Max 2 LSB INL, 50nA Sleep current, Tiny 2mm x 2mm DFN-6 Package, 30Hz Output Rate 2 LSB INL, 50nA Sleep Current, Tiny 2mm x 2mm DFN-6 Package, 60Hz Output Rate
No Latency is a trademark of Linear Technology Corporation.
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16 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 1007 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007

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